In the present study, a numerical approach for characterizing three-dimensional (3-D) electronic packages is presented, based on the steady-state solution of the thermal network method for generalized rectangular geometries, where boundary conditions are uniformly specified over specific regions of the package. As we know, the thermal-network method is very powerful on thermal analysis of electronic packaging because of its feasibility and flexibility. Accordingly, the numerical approach with thermal-network method to simulate heat transfer characteristics for 3-D package geometries becomes important in the modem microelectronic applications. The thermal analyses are presented with a general overview of the thermal network method, boundary conditions and solution procedures. Furthermore, the application of boundary conditions at the fluid-solid, package-board and layer-layer interfaces provides a means for obtaining a unique numerical result for 3-D complex electronic packages. The complex geometries found in most 3-D electronic package configurations are modeled using numerical method through the careful use of simplifying assumptions. Comparisons of the present numerical results with the existing experimental data for 3-D electronic package of pin grid arrays and multi-chip modules are made with a satisfactory agreement. Thus, the present study demonstrates that the numerical thermal-network approach can offer an accurate and efficient solution procedure for evaluating the thermal characterization of 3-D electronic packages.

1.
Ellison
G. N.
,
1976
, “
The Thermal Design of an LSI Single-Chip Package
,”
IEEE Transactions on Parts, Hybrids, and Packaging
, Vol.PHP-
12
. No.
4
, pp.
371
378
.
2.
Ellison, G. N., 1984, Thermal Computations for Electronic Equipment, van Nostrand Reinhold Co., New York.
3.
Culham
J. R.
, and
Yovanovich
M. M.
,
1997
, “
Thermal Characterization of Electronic Packages Using a Three-Dimensional Fourier Series Solution
,”
EEP
-Vol.
19–2
, In Advances in Electronic Packaging, pp.
1955
1965
,. ASME, New York, USA, July 8-13.
4.
Arbeitman, K. J., 1993, “Temperature Sensitivity to Node Spacing in ASTAP Finite Difference Modelling for Flat Cap Single- and Multi-chip Modules,” Proceedings of the 9th IEEE, Semiconductor Thermal Measurement and Management Symposium, pp.81–87.
5.
Weeks, W. T., Jimenez, A. J., Mahoney, G. W., Mehta, D., Qassemzadeh, H., and Scott, T. R., 1973, “Algorithms for ASTAP - A Network-Analysis Program,” IEEE Transactions on Circuit Theory, Vol. CT-20, No.6, November.
6.
Advanced Statistical Analysis Program (ASTAP) Reference Guide, Pub. No. LY20–0764, IBM Corporation, White Plains.
7.
Cooke, J. A., and Lee, S. W., 1989, “Finite Element Thermal Analysis of 144 Pin Plastic Flat Packs,” Proceedings of the 5th IEEE Semiconductor Thermal and Temperature Measurement Symposium, pp.59–62.
8.
Pierce, B. L., and Stumpf, H. J., 1969, “TAP-A - A Program for Computing Transient or Steady-State Temperature Distribution,” Westinghouse Astronulear Laboratory, U.S.A.
9.
Xie M. and Toh K. C., 2002, “An Adaptable Compact Thermal Model for BGA Packages,” IEEE Electronic Packaging Technology Conference, pp.304–311.
10.
EIA/JESD 51-2 Integrated Circuit Thermal Test Method Environment Conditions - Natural Convection.
11.
Loh C. V., Toh K. C., Pinjala D. and Iyer M. K., 2000, “Development of Effective Compact Models for Depopulated Ball Grid Array Packages,” 3rd Electronic Packaging Technology Conference, Singapore.
12.
Shullhan, R., Fredholm, M., Monahan, T., Agarwall, A., and Kozarek B., 1991, “Thermal Modeling and Analysis of Pin Grid Arrays and Multichip Modules,” Proceedings of the 7th IEEE Semiconductor Thermal Measurement and Management Symposium, pp.110–116, Phoenix, AZ, USA.
This content is only available via PDF.
You do not currently have access to this content.