Through-Silicon-Vias (TSVs) continue to stand out as the most promising technology for electrical interconnections in the microelectronics industry. As package size continues to decrease, TSVs offer an elegant and robust solution for vertical interconnects. They facilitate 3D die stacking while minimizing or even eliminating area consuming planar packaging, allowing for direct signal and power paths through the substrate itself. TSVs can also be fabricated from different materials to desired dimensions to handle the required current level. Plated copper is emerging as the material of choice for TSVs. In this work, electroplated copper TSVs were fabricated successfully and evaluated using cutting and polishing techniques in preparation for image capture. The detailed fabrication process and analysis of the resulting TSVs are presented in this work.
A Novel Plating Technique for Realizing Copper Filled TSVs in Silicon Wafers
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Adanur, E, Ellis, C, Dean, RN, Tuck, E, & Strembicke, D. "A Novel Plating Technique for Realizing Copper Filled TSVs in Silicon Wafers." Proceedings of the ASME 2011 International Mechanical Engineering Congress and Exposition. Volume 11: Nano and Micro Materials, Devices and Systems; Microsystems Integration. Denver, Colorado, USA. November 11–17, 2011. pp. 957-962. ASME. https://doi.org/10.1115/IMECE2011-63689
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