In this study, a simple theory for estimating the warpage of chip size packaging (CSP) during a manufacturing process is presented. A single-sided CSP which is composed of IC, a resin and a substrate is modeled for an analysis as a three-layered material. Especially, the resin and the substrate have different thermo-viscoelastic properties. When the layered body is perfectly bonded, its warpage is caused by the difference of the thermal expansion coefficient in each layer when temperature varies. The warpage of CSP for a various thicknesses of the IC and the substrate is investigated. Finally, the warpage calculated using the theory is compared with the result in experiment, and both results are well agreed with each other. Then, it is shown that the simple theoretical analysis is valid. After that, this program is extended to be able to analyze the warpage in a CoC (Chip on Chip), and the result of the analysis is then presented.

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