The effect of Cu-filled through-silicon vias (TSVs) interposers on the reliability of 3D IC integration system-in-package (SiP) is investigated in this study. Emphasis is placed on the determination of the stresses at the Cu-low-k pads on a Moore’s law chip and the creep strain energy density per cycle at the corner solder joints between the Moore’s law chip and an interposer. Also, thermal cycling tests and failure analysis results of a test vehicle is presented and discussed.

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