A thermo-mechanical analysis is carried out on a stacked die package having through silicon via technology to study the overall reliability of the package due to varying aspect ratio (size and shape) of through silicon vias, silicon die thickness, underfill thickness and underfill material properties. Through silicon via technology is one of the most rapidly developing technologies in the semiconductor industry and assures the development for the continued role of Moore’s law and multichip integration as well as packaging approaches. Wire bond and flip-chip have been in use for long time now while TSV is the latest technology of 3D integration system which is used for primary interconnection. The benefits of the use of TSV technology are increased performance, reduced form factor and cost reduction of the package. A three dimensional finite element model of a stacked package that consists of stacked dice using through silicon vias, solder interconnect, underfill, substrate and PWB is solved numerically to assess the reliability of the overall stacked package. In this analysis, stress free temperature for stacked package is kept at 125°C while room temperature is 25°C to carry out the simulation of the stresses post cure cool down of the stacked package. Stresses are calculated at the die as well as interfaces between underfill and die and underfill and substrate to assess the reliability of the overall package. A parametric study of critical geometric parameters such as aspect ratio, thickness of silicon die and underfill thickness and process parameters is carried out to minimize the maximum stresses on the overall stacked package. Recommendations are provided with respect to controlling the critical parameters such as aspect ratio, silicon thickness, underfill thickness and varying the underfill material properties (E and α) to improve the overall reliability and strength of the package.

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