Most of the electronic devices manufactured are used in daily life and with the miniaturization process of these devices, in the day to day life there is a risk of drop impact failure. It has been important to analyze and ensure the reliability of any electronic devices under every type of loading. Drop impact is not only loading that can affect reliability, but the simultaneous thermal load, moisture, convection is also acting. Smaller devices like cell phones, laptops, tablets are more prone to accidental impact loads which create board interconnects failure by frequent drop occurrence. Therefore, a multi-dimensional approach is taking place in research to study product reliability. In this paper, comprehensive study of drop and shock test is done on Quad Flat No-lead (QFN) package board of two different thickness. The computation setup is done with thermal analysis by providing power to die of the package which creates non-uniform temperature distribution during the drop testing analysis. This way drop test is coupled with a thermal load which is more realistic analysis. Our study depends on young’s modulus, density, CTE, thermal conductivity, specific heat and Poisson’s ratio of the material. Therefore, Experimental work includes material properties characterization of two boards to get temperature dependent Coefficient of thermal expansion, poison’s ratio and young’s modulus values using Thermal mechanical analyzer (TMA), the Dynamic mechanical analyzer (DMA) and Universal testing machine. Finite element analysis (FEA) method is used for computational analysis. Effect of impact loading for two boards has been done to investigate board and solder joint reliability due thickness and layer stack-ups in PCBs in environmental condition and at elevated temperature. For computational analysis, the assembly is subjected to the drop test per JEDEC standards.  The main purpose of this work is to study the impact of drop test with the powered package and how the reliability of any assembly changes with changing the stiffness of printed circuit board. The comparison of the boards has been made to understand the effect of PCB layer stack-ups, thickness, and temperature effect on the reliability of solder interconnects by considering the stress-strain generation that is induced in the PCBs during the drop test.
- Electronic and Photonic Packaging Division
A Computational Approach to Study the Impact of PCB Thickness on QFN Assembly Under Drop Testing With Package Power Supply
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Rahangdale, U, Rajmane, P, Misrak, A, & Agonafer, D. "A Computational Approach to Study the Impact of PCB Thickness on QFN Assembly Under Drop Testing With Package Power Supply." Proceedings of the ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2017 Conference on Information Storage and Processing Systems. ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. San Francisco, California, USA. August 29–September 1, 2017. V001T01A019. ASME. https://doi.org/10.1115/IPACK2017-74278
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