While 3D integrated circuits (3D ICs) offer a great enhancement in performance, the increased power density, nonuniform power distribution and high thermal resistance pose significant thermal management challenges. Thermal through-silicon-vias (TTSVs) are TSVs that do not carry signal but facilitate heat transfer across stacked dies. The use of TTSVs occupies extra space and extends the distance between IC blocks leading to an increase in signal delay. The trade-offs between the temperature and wirelength are evident in the TTSV placement. In this paper, we propose a hierarchical approach to optimize the floorplan of a 3D Nehalem-based multicore processor. The floorplan of a single core is optimized using simulated annealing (SA)-based algorithm and the floorplan of the entire 3D IC is generated based on the symmetric operation. Our simulation results show that the peak temperature decreases with the TTSV area overhead and the wirelength strongly depends on the TTSV placement. Compared to the SA-optimized floorplan with no TTSVs, the SA-optimized floorplans with TTSV offer 6–15 °C more reduction in peak temperature while keeping the wirelength increase from 10 % to 40 % at 2–20 % TTSV area overheads. We also evaluate the effects of anisotropic thermal transport in TTSVs and show that the lateral thermal conductivity of TTSV has a significant impact on the peak temperature of 3D ICs.