One key concern that arises from scaling of device interconnects with increasing power density requirements is electromigration (EM). On the other hand, thermal cycling fatigue has always been a reliability challenge in solder interconnects. Variations in device temperature caused by environmental or operating conditions induce stress in solders, as they usually connect two components with different coefficients of thermal expansion (CTE). These thermally induced stresses may lead to crack formation within the solders. The combination of EM effects and thermal cycling add to the complexity of the reliability estimation for high current density applications.
In this work, a novel test setup has been designed and developed to estimate the reliability of solder interconnects under high current density, while a constant tensile stress is also applied to the solder interconnect. The test set up offers the ability to test up to four samples at the same time. Additionally, the test samples are fabricated with two copper wires connected by Pb/Sn solder to imitate copper UBM in a flip-chip bonding connection. Strain in solder is measured by monitoring the elongation of the wire during testing, while failure of the connection is detected by continuous monitoring of the electrical resistance. The experiment is conducted for conditions including pure tensile stress, pure EM and coupled EM and tensile stress where a significant reduction in life-time is observed for the coupled degradation effects. Comparing the experimental results of different current densities at different stress levels will help in identifying the nature of degradation in solders, which will help inform the drive for miniaturization.