The synthesis of vertically aligned carbon nanotubes (CNTs), also referred to as CNT forest, by chemical vapor deposition (CVD) is an intricate process that is sensitive to multiple factors other than control of temperature, pressure, and gas flows. In particular, growth is highly sensitive to factors like ambient humidity, as well as small quantities of oxygen-containing species and carbon deposits inside the reactor. These typically uncontrolled factors significantly affect growth reproducibility and hinders the fundamental study of process-structure-property relationship for these emerging materials. Accordingly, universally applicable design modifications and process steps toward improve growth consistency are sought after. In this study, we introduce two new modifications to our custom-designed multizone rapid thermal CVD reactor and demonstrate their impact on growth: (1) reconfiguring the inlet gas plumbing to add a gas purifier to the helium (He) line, and (2) designing a new support wafer for consistent loading of substrates. We use statistical analysis to test the effectiveness of these modifications in improving growth and reducing variability of both CNT forest height and density. Analysis of our experimental results and hypothesis testing show that combining the implementation of He purifier with the redesigned support wafer increases forest height and reduces the variability in height (17-folds), both at statistically significant and practically significant levels.

Recent investigations on the fabrication of ultra-thin silicon (Si) wafers using wire-electrical discharge machining (wire-EDM) were observed to possess some inherent limitations. This includes severe thermal damage, kerf-loss, and low slicing rate, which could be detrimental towards realizing actual practical applications. The extent of thermal damage, kerf-loss, and slicing rate largely depends on the process parameters such as open voltage (OV), servo voltage (SV), and pulse on-time (T on ). Therefore, choosing the optimal parameters that pertain to minimum thermal damage and kerf-loss while maintaining a higher slicing rate is the key to further excel in the fabrication of Si wafers using wire-EDM. Therefore, the present study is an effort to analyze and identify the optimal parameters that relate to the most effective Si slicing in wire-EDM. A central composite design (CCD) based response surface methodology (RSM) was used for optimizing the process parameters. The capability to slice Si wafers in wire-EDM was observed to be highly influenced by the discharge energy, which had a positive impact on the overall responses. The severity of thermal damages was observed to be mainly dominated by the variation in open voltage and T on due to the high diffusion of thermal energy into the workpiece, which led to intense melting and subsequent re-solidification. The parametric optimization resulted in OV = 84.32 V, SV = 42.98 V and T on = 0.62 μs as the most feasible parameter that relates to comparatively high slicing rate (0.65 mm/min), low kerf-loss (280 μm) and thermal damage (18 μm) for a given machine. In general, with a decrease in spark energy slicing rate and thermal damage decreases whereas, kerf-loss increases. When spark energy decreases by 83%, there is a nearly 55% decrease in slicing rate and thermal damage and a 10% increase in kerf-loss.

Bottoms-up cost analysis has been a mainstay of commoditized industry and manufacturing processes for years, however a holistic objective supply chain analysis to inform research and investment in the development of early stage technologies has not. The potential for rapid adoption of wide bandgap (WBG) semiconductors, specifically silicon carbide (SiC), highlights a need to understand the drivers of location-specific manufacturing cost, global supply chains, and plant location decisions. Further, ongoing research and investment, necessitates analytical analysis to help inform the roadmap of SiC technologies. In collaboration with PowerAmerica the project explores the bottoms-up cost analysis of wafers, devices, modules, and variable frequency motor drives at the anticipated manufacturing levels. Leveraging these models, it outlines how the cost reduction potential of proposed research advances can be quantified.

The high quality surface can exhibit the irreplaceable application of single crystal silicon carbide in the fields of optoelectronic devices, integrated circuits and semiconductor. However, high hardness and remarkable chemical inertness lead to great difficulty to the smoothing process of silicon carbide. Therefore, the research presented in this paper attempts to smooth silicon carbide wafer with photocatalysis assisted chemical mechanical polishing (PCMP) by using of the powerful oxidability of UV photo-excited hydroxyl radical on surface of nano-TiO 2 particles. Mechanical lapping was using for rough polishing, and a material removal model was proposed for mechanical lapping to optimize the polishing process. Several photocatalysis assisted chemical mechanical polishing slurries were compared to achieve fine surface. The theoretical analysis and experimental results indicate that the material removal rate of lapping process decreases in index form with the decreasing of abrasive size, which corresponds with the model developed. After processed with mechanical lapping for 1.5 hours and subsequent photocatalysis assisted chemical mechanical polishing for 2 hours, the silicon carbide wafer obtains a high quality surface with the surface roughness at Ra 0.528 nm The material removal rate is 0.96 μm/h in fine polishing process, which is significantly influenced by factors such as ultraviolet irradiation, electron capture agent (H 2 O 2 ) and acidic environment. This combined method can effectively reduce the surface roughness and improve the polishing efficiency on silicon carbide and other hard-inert materials.

The key performance indicators in Chemical Mechanical Planarization (CMP) processes are usually assessed by measuring the material removal rate (MRR) and Within-Wafer-Nonuniformity (WIWNU), which are vitally dependent on the processing variables including down pressure, wafer rotation, polishing pad rotation, polishing table rotation, slurry flow, and the condition of the polishing pad etc. MRR is critical to the WIWNU also since MRR can infer the end-point in the polishing process. In this study, empirical approaches were conducted to model the MRR with the production CMP settings. With the collected data from real semiconductor manufacturing processes, correlation and principle component analysis (PCA) were conducted to select the features mostly related to the CMP processes, then neural network (NN) and adaptive neuro fuzzy inference system (ANFIS) based models were proposed to understand processing variables in CMP process and estimate the MRR. The NN and ANFIS models were compared on the performance metrics of 1) mean square error (MSE), and determination coefficient (R 2 ) based on bootstrap. The bootstrap based evaluation shows that NN achieved a MSE of 9.68e03 with the R 2 value of 0.81 in the training stage and MSE of 9.59e3 with the R 2 value of 0.81 in the validation stage; ANFIS achieved a MSE of 126.24 with the R 2 value of 0.9102 in the training stage and MSE of 6.17e4 with the R 2 value of 0.3133 in the validation stage. The empirical models are promising to be integrated with the data-driven based control of CMP processes.

Maskless nanolithography is an agile and cost effective approach if their throughputs can be scaled for mass production purposes. Using plasmonic nanolithography approach, direct pattern writing was successfully demonstrated with 22 nm half-pitch at high speed. Plasmonic nanolithography uses an array of plasmonic lenses to directly pattern features on a rotating substrate. Taking the advantage of air bearing surface techniques, the system can expose the wafer pixel by pixel with a speed of ∼10 m/s, much faster than any conventional scanning based lithography system. It is a low-cost, high-throughput maskless approach for the next generation lithography and also for the emerging nanotechnology applications, such as nanoscale metrology and imaging. A critical part of the PNL is to use plasmonic lens to deliver highly concentrated optical power at nanoscale. We have demonstrated such nanoscale process and achieved 22 nm resolution. Here, we report our recent efforts of designing new plasmonic nanofocusing structures that is capable of achieving optical confinement below 20 nm which can potentially support direct patterning at sub-10nm resolution.

One of the major challenges in nanoscale manufacturing is defect control because it is difficult to measure nanoscale features in-line with the manufacturing process. Optical inspection typically is not an option at the nanoscale level due to the diffraction limit of light, and without inspection high scrap rates can occur. Therefore, this paper presents an atomic force microscopy (AFM)-based inspection system that can be rapidly implemented in-line with other nanomanufacturing processes. Atomic force microscopy is capable of producing very high resolution (sub-nm-scale) surface topology measurements and is widely utilized in scientific and industrial applications, but has not been implemented in-line with manufacturing systems, primarily because of the large setup time typically required to take an AFM measurement. In order to overcome this limitation, we have developed a single-chip-AFM-based inspection system where a wafer can be precisely and repeatably loaded into the setup and measurements can be taken in under 60 seconds. This inspection system consists of several single-chip AFMs integrated into a positioning stage to make measurements at multiple spots on a wafer at the same time. Each single-chip AFM is a MEMS device that is approximately 2 mm wide by 1 mm tall and is capable of scanning a 10 micron by 10 micron area. Thermal actuators in the MEMS device are used to do the scanning in both the x and y directions as well as to excite the z axis of the AFM so that it can be run in taping mode. Each AFM is attached to a flexure stage in the top plate of the inspection system so that the AFM can be precisely moved to the desired inspection location on the wafer. The flexure plate is coupled to the inspection plate using a kinematic coupling so that the flexure plate can be precisely located with respect to the inspection plate after each loading operation. In order to take a measurement, the flexure plate is removed from the inspection plate, a wafer is loaded into the inspection plate using an exactly constrained, passive alignment system, and the flexure plate is then placed back onto the inspection plate. This brings the AFMs back into contact with the surface that is to be measured and the AFMs can then start taking measurements without any additional alignment operations. The overall measurement procedure takes less than one minute, which is faster than most nanomanufacturing processes. This guarantees that the inspection step will not be the bottleneck in the manufacturing process.

One of the major challenges in producing highly accurate graphene-based nanoelectromechanical (NEMS) resonators is the poor fabrication repeatability of graphene-based NEMS devices due to small variations in the residual stress and initial tension of the graphene film. This has meant that graphene-based nanoelectromechanical resonators tend to have large variations in natural frequency and quality factor from device to device. This poor repeatability makes it impossible to use these resonators to make accurate, high-precision force and displacement sensors or electromechanical filters. However, by actively controlling the tension on the graphene resonator it is possible both to increase repeatability between devices and to increase the force/mass sensitivity of the nanoelectromechanical resonators produced. Such tension control makes it possible to produce electrometrical filters that can be precisely tuned over a frequency range of up to several orders-of-magnitude. In order to controllably strain the graphene resonator, a microelectromechanical system (MEMS) is be used to apply tension to the graphene. The MEMS device consists of a graphene resonator connected between a set of gold electrodes. Each gold electrode is located on a different MEMS stage. Each stage is connected to a set of flexural bearings which are used to guide the motion of the stage. The displacement stage is actuated using a thermal actuator that allows a uniform and constant tension to be applied to the graphene resonator. The displacement of the actuator and the tension applied to the graphene are measured using a pair of differential capacitive actuators. The resonator is actuated electrostatically using the electrical back gate, and the resonant frequency is measured from the change in conductance of the graphene as it approaches resonance. Using this setup, it is possible to tune the natural frequency of the graphene resonator with high precision and accuracy. In addition to designing devices that can compensate for manufacturing errors in nanomanufactured devices, this paper will present several methods that can greatly expand the scope and rate at which nanomaterials-based devices can be fabricated. For example, this paper will present a transfer-free, wafer-scale manufacturing process that can be used to produce suspended graphene-based devices such as the graphene-based NEMS resonators. This new method involves the growth of graphene directly on the device wafer and release of the graphene-based device through etching of the copper catalyst layer. This method replaces traditional graphene fabrication methods, such as mechanical exfoliation, electron beam lithography, or transfer from copper foils, which are slow and require a transfer step that is the source of much of inconsistency in suspended graphene-based devices. Therefore, these new transfer-free, wafer-scale fabrication methods offer the potential to increase the throughput, yield, and repeatability of manufacturing processes for graphene resonators while reducing manufacturing costs and complexity.

This paper presents the research on the machinability studies in micro-milling of (001) silicon wafer. Excessive generation of undesirable surface and subsurface damages such as surface edge chipping often occurs when machined at depth of cut of several hundreds of microns. Ideal machining strategy to reduce the generation of edge chipping is required. Investigations on the effect of machining conditions on the cutting performances and size effect on the specific cutting energy in silicon micro-milling were conducted. These investigations provide understandings on the behavior of cutting mechanism during machining and helps to identify suitable machining parameters for fracture free machining using diamond end mills. Full slot milling were performed along <100> and <110> directions on a (001) surface wafer under various machining conditions. Results show that machined surfaces along <100> were of better quality than those along <110> and is in agreement with previous studies. Furthermore, good machining quality was achieved when machined at depth of cut of 10 μm or feed per tooth of 0.075 μm/tooth, regardless of the machining conditions. In addition, investigation for the size effect on specific cutting energy also shows that brittle mode machining begins when feed per tooth increases beyond 0.4 μm/tooth.

Maskless nanolithography is an agile and cost effective approach if their throughputs can be scaled for mass production purposes. Using plasmonic nanolithography (PNL) approach, direct pattern writing was successfully demonstrated with around 20 nm half-pitch at high speed. Here, we report our recent efforts of implementing a high-throughput PNL prototype system with unique metrology and control features, which are designed to use an array of plasmonic lenses to pattern sub-100 nm features on a rotating substrate. Taking the advantage of air bearing surface techniques, the system can expose the wafer pixel by pixel with a speed of ∼10 m/s, much faster than any conventional scanning based lithography system. It is a low-cost, high-throughput maskless approach for the next generation lithography and also for the emerging nanotechnology applications, such as nanoscale metrology and imaging.

Motivated by previous work on three-dimensional (3D) fabrication inside dielectrics, we report experimental results of 3D modification inside intrinsic silicon wafers using laser pulses with 1.55 μm wavelength and 3.5 ns pulse duration. Permanent modification in the form of lines is generated inside silicon by tightly focusing and continuously scanning the laser beam inside samples, without introducing surface damage. Cross sections of these lines are observed after cleaving the samples, and are further analyzed after mechanical polishing followed by chemical etching. With the objective lens corrected for spherical aberration, tight focusing inside silicon is achieved and the optimal focal depth is identified. The laser-induced modification has a triangular shape and appears in front of the geometrical focus, suggesting significant absorption in those regions and resulting in reduced energy density. The morphology of modified regions is found to be dependent on the laser polarization.

Silicon is an excellent transparent material for building IR micro-optical elements such as holographic and blazed gratings, and curvilinear micro-lenses. Shaping this material in 3D with mirror quality finish and single-digit microscale resolution is challenging due to its brittleness and high-melting point. To achieve these patterning characteristics, electron-beam grayscale lithography is typically selected to pattern a 2.5D feature onto a resist thin-film. Subsequently, the film features are transferred into the underlying silicon substrate by deep-reactive ion etching (DRIE) [1]. Small variations in the resist thickness lead to large shape distortions and reduced patterning repeatability. Further, the direct-write nature of e-beam lithography provides for slow throughput. Developing an alternative, parallel and scalable method to nanopatterning silicon with 2.5D geometrical control may impact emerging areas such as the design of sub-wavelength photonic and micro-optic elements for silicon photonics applications. Micro and nanoscale patterning of inorganic semiconductors (e.g. Silicon) requires traditional micromachining processes such as plasma-assisted etching (e.g. DRIE) and wet-etching (e.g. KOH etching). Neither of the aforementioned processes offer the capability to control the geometry in 3D with resolution in the nanoscale range. Thus, it is desirable to develop a low-temperature, low-stress and ambient approach to nanostructuring silicon in 3D. Wet etching approaches are good candidates for achieving such goal because they bypass the need for high-temperature processing and stressing materials beyond the elastic limit. Yet, they still rely on lithographical steps and offer limited sidewall control, restricting the scope of features it can produce. In recent literature, catalyst-based wet etching processes such as metal-assisted chemical etching (MACE) have been shown to pattern high-aspect ratio structures in semiconductors [2–3]. Some researchers have achieved control over the etch profile and etching direction, generating a limited set of interesting 3D objects [4–6]. The degrees of freedom in MACE patterning are still highly constrained due to limited control of the catalyst motion. Additionally, thin-film based MACE relies on intermediate 2D masking steps to pattern the catalyst which are often lithographical. Thus, this indirect approach to patterning silicon increases lead time and processing costs. In this paper, Mac-imprint, a direct imprint configuration of MACE, is introduced to overcome these fundamental barriers. It relies on the use of a catalytic stamp immersed in the etchant and brought against a silicon chip to selectively dissolve it at contact points. Stamps can be reused multiple times to pattern substrates with lifetimes that are dependent solely on its chemical and mechanical degradation. This process is inherently non-lithographic and occurs at room temperature. As a demonstration of its high-resolution capabilities, silicon wafers were patterned with a sinusoidal wave whose pitch and amplitude were 1 μm and 250 nm, respectively. The patterned surface RMS error from the ideal surface was measured to be 13 nm. The key drawback of this approach is the generation of porous defects near the vicinity of the contact interface between stamp and substrate. Its spatial distribution is qualitatively discussed in the context of the diffusion model of MACE [7].

In this study, single point diamond turning (SPDT) is coupled with the micro-laser assisted machining (μ-LAM) technique. The μ-LAM system is used to preferentially heat and thermally soften the work piece material in contact with a diamond cutting tool. In μ-LAM the laser and cutting tool are integrated into a single package, i.e. the laser energy is delivered by a single mode fiber laser to and through a diamond cutting tool. This hybrid method can potentially increase the critical depth of cut (DoC), i.e., a larger ductile-to-brittle transition (DBT) depth, in ductile regime machining, resulting in a higher material removal rate (MRR). An IR continuous wave (CW) fiber laser, wavelength of 1064nm and max power of 100W with a beam diameter of 10μm, is used in this investigation. In the current study SPDT tests were employed on single crystal silicon (Si) wafer which is very brittle and hard to machine by conventional methods. Different outputs such as surface roughness and depth of cut for different set of experiments were analyzed. Results show that an unpolished surface of a Si wafer can be machined in one pass to get a very good surface finish. The Ra was brought down from 1.2μm to 275nm only in one pass which is a very promising result for machining the Si wafer.

Sapphire or mono-crystalline aluminum oxide wafers have been popularly adopted as the substrates of epi-layer process for the rapid growing demands of high-brightness light emitting diode (HB LED) industry. The HB LED devices for solid-state illumination have attracted immerse investigation of sub-surface crack problem induced in sapphire wafer processing. The diamond lapping has been recognized as a critical process for affecting the final polishing of sapphire wafers. This paper is to investigate the sub-surface damage layer induced by the diamond slurry lapping processes of sapphire wafers with two kinds of benchmark diamond slurries with different properties. All test wafers have been measured by dial gauge to observe the variation of thickness first and then the surface topography and subsurface properties have been inspected by coherence interferometer, CCI-Lite (Taylor Hobson, UK) instrument and then dual-focus focused ion beam, FIB (FEI Quanta 3D FEG) for sub-surface crack observation. The diamond slurry is composed with diamond abrasive grits and carrier for lapping with resin copper grooved plate. In this study, two slurries are noted as F and S both with the nominal diamond grit size 3 micron. The carriers are glycol based with viscosity ranged around 20 cP in room temperature and the viscosity-temperature plots have been measured for such slurry. Experimental results have shown that the 3D average surface roughness, S a is obtained as 9.12 nm for sapphire wafer lapped by F slurry and as 6.63 nm lapped by S slurry. Thus the relationship of particle size distribution (PSD) of diamond grits and also the viscosity-temperature effect can be considered as key factors to MRR and surface quality of diamond lapping process of sapphire wafers. The sub-surface cracks can then be observed by FIB instrument and then quantified to evaluate the effects of diamond lapping process in order to shorten the further polishing time.

The cutting performance of the PZT/Si wafer micro milling was investigated by using the diamond coated micro end mill. At the same time, the cutting force and AE signals collected during cutting were also investigated to identify their capability of monitoring the surface condition and ductile/brittle cutting mode. To analyze the cutting performance of PZT thin film and corresponding signals, an experiment was conducted on a micro-machining equipment with resolution of 1 um. The PZT thin film with thickness of around 1 um was deposited on the Si wafer by a Sol-Gel method. During cutting, the AE signal was collected by an AE sensor clamped on the top of wafer, and the cutting force was collected by a Kistler 9256C dynamometer installed under a vacuum chuck. After the cutting, the finished surface was investigated by a white light interferometer system, and the chip was also investigated by a scanning electronic microscopic (SEM). The results show that the while light interferometer can be used to identify the cracked spot on the bottom of the machined surface. For the cutting mode analysis, the ductile mode cutting cannot be reached for the PZT thin film machining in this study. However, it can be obtained for Si wafer at the same cutting condition. Moreover, the RMS cutting force for PZT machining is higher than the Si wafer machining and its surface finish is not as good as in cutting the pure Si wafer. In analyzing the collected AE and cutting force signals, the AE signal, the time domain cutting force signals, and the RMS cutting force signals demonstrate their high correlation with the ductile/brittle cutting mode and surface condition.

In this paper, the femtosecond laser ablation of silicon is investigated by a two-dimensional hydrodynamic model. The ablation depth of the silicon wafer ablated in air at different laser intensities is calculated, and the corresponding experimental measurements are carried out for validation. Two different ablation regimes have been identified by varying the laser fluence. While two-photon absorption dominates in the low fluence regime (< 2 J/cm 2 ), electron heat diffusion is a major energy transport mechanism at higher laser fluences (> 2 J/cm 2 ). The ablation efficiency first increases with the laser fluence, and reaches the peak value at the laser fluence around 8 J/cm 2 . It starts to drop when the laser fluence further increases, because of the early plasma absorption of the laser beam energy.

Slurry wire saw has been utilized to slice the brittle semiconductor wafer substrates for over 20 years. However, the complicated slicing process limits the further studies and advances of this exclusive slicing tool for big wafers. In this study, a numerical model of the slurry wire sawing process was developed based on the mechanism of brittle indentation cracks. The simulation results illustrate how the factors such as wire speed, wire tension, and feed rate of the ingot affect the slicing conditions including the bow angles of the wire and the local normal loads on both the workpiece and the wire. In addition, the results show that the steady-state condition would be reached via overshooting or non-overshooting approach based on the slicing parameters. A higher wire speed is suggested to reduce the bow angles and local loads during slicing process. However, the limitation of the wire speed depends on the material of the wire and the specification of the wire saw machine.

Chemical mechanical planarization (CMP) is widely used to planarize semiconductor wafers and smooth the wafer surface. In CMP, a diamond disc conditioner is used to condition (or dress) a polishing pad to restore the pad performance. In this paper, a surface element method is proposed to develop a mathematic model to predict the pad surface shape resulted from diamond disc conditioning. The developed model is then validated by published experimental data. Results show that the model is effective to simulate the diamond disc conditioning process and predict the pad surface shape.

In semiconductor fabrication processes, reliable feature extraction and condition monitoring is critical to understanding equipment degradation and implementing the proper maintenance decisions. This paper presents an integrated feature extraction and equipment monitoring approach based on standard built-in sensors from a modern 300mm-technology industrial Plasma Enhanced Chemical Vapor Deposition (PECVD) tool. Linear Discriminant Analysis was utilized to determine the set of dynamic features that are the most sensitive to different tool conditions brought about by chamber cleaning. Gaussian Mixture Models of the dynamic feature distributions were used to statistically quantify changes of these features as the condition of the tool changed. Data was collected in the facilities of a well-known microelectronics manufacturer from a PECVD tool used for depositing various thin films on silicon wafers, which is one of the key steps in semiconductor manufacturing. Dynamic features coming from the radio frequency (RF) plasma power generator, matching capacitors, pedestal temperature, and chamber temperature sensors were shown to consistently have significant statistical changes as a consequence of repeated cleaning cycles, indicating physical connections to the chamber condition.

This paper presents a novel method to achieve high yield assembly of millimeter-scale thin silicon chips from an air-water interface. Surface functionalized silicon parts (1×1 mm 2 with 100 μm thickness) assemble in preprogrammed hydrophilic locations on a wafer substrate with self-alignment. We optimize the process and design factors systematically using DOE (Design of Experiment) that leads to high yield (close to 100 %). This paper also presents an experimental and theoretical study of a high yield self-assembly process with programmable template. An analysis of the method is presented with an emphasis on the combined effect of substrate tilting angle and part size on fluidic assembly at an air-water interface. For 1×1, 3×3 and 5×5 mm 2 parts with 100 μm thickness, the maximum substrate tilting angles are experimentally determined and the surface tension induced torques are calculated based on the developed model. The result indicates that there is a limit on the lateral size of the parts that can be assembled when we use one substrate tilting angle. Based on our analysis, we propose a novel method that is capable of assembling parts of higher lateral dimensions using parametric changes in substrate tilting angle.