Skip to Main Content
Skip Nav Destination
ASME Press Select Proceedings

International Conference on Computer Technology and Development, 3rd (ICCTD 2011)

By
Jianhong Zhou
Jianhong Zhou
Search for other works by this author on:
ISBN:
9780791859919
No. of Pages:
2000
Publisher:
ASME Press
Publication date:
2011

This paper proposed a novel half-pixel interpolation implementation scheme of H.264/AVC based on the resource of C64x+ DSP (Digital signal processor) and characteristic of cache on TMS320C64x+ platform. Firstly, the theory of H.264 half-pixel interpolation was analyzed. Then half-pixel horizontal interpolation process was optimized with a parallel computing pattern. For further reducing the cache miss rate and cache bank conflicts, Half-pixel vertical interpolation process was equally transformed to matrix transposition and horizontal interpolation process. Finally, the optimized scheme were realized by linear assembly language, Simulation results show that the optimized scheme was effective and could result in 3.5 times speed...

Abstract
Key Words
I Introduction
II. Half-Pixel Interpolation in H.264/AVC
III. Half-Pixel Interpolation Optimization
IV. Experimental Results
V. Summaries
References
This content is only available via PDF.
You do not currently have access to this chapter.
Close Modal

or Create an Account

Close Modal
Close Modal