In this paper, an “interfacial boundary volume” based damage criterion was proposed in combination with the modified Coffin-Manson model to predict solder fatigue. This criterion assumes that mainly, the behavior of the thin solder layer at chip pad interface contributes to the solder fatigue, not the whole solder joint or the averaged strains from randomly selected elements. The damage parameter was thus calculated by averaging the visco-plastic strain range over the interfacial boundary layer volume in the solder and later related to the corresponding fatigue life of experimental test through least-squares curves fitting to determine the empirical coefficients in the Coffin-Manson equation. As a demonstrator, the solder joint fatigue in wafer level chip scale packaging under thermal shock loading was analyzed. An appropriate constitutive relation from Darveaux was used to model the inelastic deformation of the solder alloy, and the different stress-strain responses resulting from different designs were calculated. The analysis results were used to develop the empirical fatigue model based on the interfacial boundary volume damage criterion and then this fatigue model was used for prediction. The fatigue lives of chip scale packaging with variable solder land size and component size were analyzed using this model. The prediction results match well with those from experimental tests. For this demonstrator, it was also shown that the empirical model based on the interfacial boundary volume criterion was more accurate than the models obtained from other strain averaging methods.
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e-mail: Zhao.xiu.juan@philips.com
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December 2003
Technical Papers
Solders Fatigue Prediction Using Interfacial Boundary Volume Criterion
X. J. Zhao,
e-mail: Zhao.xiu.juan@philips.com
X. J. Zhao
CFT-AP/Philips Electronics Singapore, 620A, Lorong 1 Toa Payoh, 319762, Singapore
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G. Q. Zhang,
G. Q. Zhang
CFT/Philips, P.O. Box 218, 5600 MD Eindhoven, The Netherlands
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J. F. J. M. Caers,
J. F. J. M. Caers
CFT-AP/Philips Electronics Singapore, 620A, Lorong 1 Toa Payoh, 319762, Singapore
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L. J. Ernst
L. J. Ernst
Delft University of Technology, 2600 GA Delft, The Netherlands
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X. J. Zhao
CFT-AP/Philips Electronics Singapore, 620A, Lorong 1 Toa Payoh, 319762, Singapore
e-mail: Zhao.xiu.juan@philips.com
G. Q. Zhang
CFT/Philips, P.O. Box 218, 5600 MD Eindhoven, The Netherlands
J. F. J. M. Caers
CFT-AP/Philips Electronics Singapore, 620A, Lorong 1 Toa Payoh, 319762, Singapore
L. J. Ernst
Delft University of Technology, 2600 GA Delft, The Netherlands
Contributed by the Electronic and Photonic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received November 2002. Associate Editor: L. Ernst.
J. Electron. Packag. Dec 2003, 125(4): 582-588 (7 pages)
Published Online: December 15, 2003
Article history
Received:
November 1, 2002
Online:
December 15, 2003
Citation
Zhao, X. J., Zhang, G. Q., Caers, J. F. J. M., and Ernst, L. J. (December 15, 2003). "Solders Fatigue Prediction Using Interfacial Boundary Volume Criterion ." ASME. J. Electron. Packag. December 2003; 125(4): 582–588. https://doi.org/10.1115/1.1604160
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