In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.
Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions
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Wang, T. H., Lee, C., Lai, Y., and Lin, Y. (October 7, 2005). "Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions." ASME. J. Electron. Packag. September 2006; 128(3): 281–284. https://doi.org/10.1115/1.2229229
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