The objective of this study is to understand the effects of various parameters involved in the chip design and cooling on the occurrence of hot spots on a multicore processor chip. The thermal environment for the die is determined by the cooling design which differs distinctly between different classes of electronic equipment. In the present study, like many other hot spot studies, the effective heat transfer coefficient represents the thermal environment for the die, but, its representative values are derived for different cooling schemes in order to examine in what classes of electronic equipment the hot spot concern grows. The cooling modes under study are high-performance air-cooling, high-performance liquid-cooling, conventional air-cooling, and oil-cooling in infrared radiation (IR) thermography setup. Temperature calculations were performed on a model which is designed to facilitate the study of several questions that have not been fully addressed in the existing literature. These questions are concerned with the granularity of power and temperature distributions, thermal interactions between circuits on the die, the roles of on-chip wiring layer and the buried dioxide in heat spreading, and the mechanism of producing temperature contrast across the die. The main results of calculations are the temperature of the target spot and the temperature contrast across the die. Temperature contrasts are predicted in a range 10–25 K, and the results indicate that a major part of the temperature contrast is formed at a granularity corresponding to the size of functional units on actual microprocessor chips. At a fine granularity level and under a scenario of high power concentration, the on-chip wiring layer and the buried oxide play some roles in heat spreading, but their impact on the temperature is generally small. However, the details of circuits need to be taken into account in future studies in order to investigate the possibility of nanometer-scale hot spots. Attention is also called to the need to understand the effect of temperature nonuniformity on the processor performance for which low temperature at inactive cells makes a major contribution. In contrast to the situation for the die under forced convection cooling, the die in passively cooled compact equipment is in distinctly different thermal environment. Strong thermal coupling between the die and the system structure necessitates the integration of package and system level analysis with the die-level analysis.
Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received February 26, 2012; final manuscript received November 7, 2012; published online March 28, 2013. Assoc. Editor: Stephen McKeown.
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Nakayama, W. (March 28, 2013). "Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies." ASME. J. Electron. Packag. June 2013; 135(2): 021003. https://doi.org/10.1115/1.4023292
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