Interconnect Fatigue Failure Parameter Isolation for Power Device Reliability Prediction in Alternative Accelerated Mechanical Cycling Test

In this work, a rapid and low-cost accelerated reliability test methodology which was designed to simulate mechanical stresses induced in flip–chip bonded devices during the thermal cycling reliability test under isothermal conditions, is introduced and demonstrated using power device analogous test chips. By stressing these devices in a controlled environment, mechanical stresses become decoupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device relevant, flip–chip solder interconnects while monitoring for failure. Herein, finite element analysis (FEA) is used to extract various damage metrics of different solder materials, including PbSn37/63, SAC305, and nanosilver, in both thermal operation and the introduced alternative mechanical testing conditions. Plastic work density and strain are calculated in the critical solder interconnects as factors that indicate the amount of the damage accumulation per cycle during the mechanical cycling, thermal cycling, and power cycling tests. The number of cycles to failure for each test was calculated using the fatigue life model developed by Darveaux for eutectic PbSn solder, while for SAC305 Syed's method was used, and for nanosilver, the Knoerr et al. equations are applied. The effects of environmental temperature and shearing force frequency were studied for the mechanical cycling reliability test, where a modified Norris–Landzberg equation for mechanical cycling tests was explored using the simulation results. Finally, comparing the mechanical cycling with the equivalent thermal cycling and power cycling demonstrated a significant reduction in required test duration to achieve a reliability estimation.