The high current densities in today's microelectronic devices and microchips lead to hotspot formations and other adverse effects on their performance. Therefore, a computational tool is needed to not only analyze but also accurately predict spatial and temporal temperature distribution while minimizing the computational effort within the chip architecture. In this study, a proper orthogonal decomposition (POD)-Galerkin projection-based reduced order model (ROM) was developed for modeling transient heat transfer in three-dimensional (3D) microchip interconnects. comsol software was used for producing the required data for ROM and for verifying the results. The developed technique has the ability to provide accurate results for various boundary conditions on the chip and interconnects domain and is capable of providing accurate results for nonlinear conditions, where thermal conductivity is temperature dependent. It is demonstrated in this work that a limited number of observations are sufficient for mapping out the entire evolution of temperature field within the domain for transient boundary. Furthermore, the accuracy of the results obtained from the developed ROM and the stability of accuracy over time is investigated. Finally, it is shown that the developed technique provides a 60-fold reduction in simulation time compared to finite element techniques.

Intermittent failures and no fault found (NFF) phenomena are a concern in electronic systems because of their unpredictable nature and irregular occurrence. They can impose significant costs for companies, damage the reputation of a company, or be catastrophic in systems such as nuclear plants or avionics. Intermittent failures in systems can be attributed to hardware failures or software failures. In order to diagnose and mitigate the intermittent failures in systems, the nature and the root cause of these failures have to be understood. In this paper we have reviewed the current literature concerning intermittent failures and have a comprehensive study on how these failures happen, how to detect them and how to mitigate them.

Comprehensive analysis of microelectronic cooling systems utilizing thermoelectric modules is time consuming because it involves solving many parametric equations, which require solving complex mathematical equations or the assistance of an expensive computation-fluid-dynamic software. In this study, a modified-graphical method (MGM) based on a previous study by Lineykin and Ben-Yaakov is proposed to analyze an active cooling system using thermoelectric modules. The MGM provides quicker visualization of the cooling requirement such as the optimum operating currents, temperature of the hot side, and coefficient of performance without the need of using any manufacturer’s proprietary data. In addition, the MGM is designed to analyze a multidimensional-heat-transfer-system utilizing thermoelectric modules (Phan, H., and Agonafer, D., 2010, “Experimental Analysis Model of an Active Cooling Method for 3D-ICs Utilizing Multidimensional Configured Thermoelectric Coolers,” ASME J. Electron. Packag. 132 (2), p. 024501).

Background: This paper presents a reduced mathematical model using a practical numerical formulation of the thermal behavior of an integrated power electronics module (IPEM). This model is based on the expanded lumped thermal capacitance method (LTCM), in which the number of variables involved in the analysis of heat transfer is reduced only to time. Method of Approach: By applying the LTCM, a simple, nonspatial, but highly nonlinear model is obtained for the case of the IPEM Generation II. Steady and transient results of the model are validated against results from a three-dimensional, transient thermal analysis software tool, FLOTHERM™ 3.1. The electrothermal coupling was obtained by implementing the reduced-order thermal model into the SABER™ circuit simulator. Two experimental setups, for low- and high-speed thermal responses, were developed and used to calibrate the reduced model with actual data. Results: The comparison of the LTCM model implemented in a Generation II IPEM with FLOTHERM 3.1 results compared very favorably in terms of accuracy and efficiency, reducing the computational time significantly. Additional validations of the reduced thermal model were made using experiment data for the low-speed thermal response at different constant powers, and good agreement was demonstrated in all cases. A comparison between SABER™ simulations, which incorporated the proposed LTCM, and the fast thermal experimental response results is also presented to validate the dynamic electrothermal model response, and excellent agreement was found for this case. Conclusions: The good agreement found for all three cases presented, the three-dimensional, transient numerical formulation, and the low- and high-speed experimental data indicates that reduced electrothermal models are an excellent alterative for design methodologies of new generations of IPEMs.

On January 1, 2000, the European project PROFIT commenced as a follow up to the successfully finished EC-funded projects DELPHI, SEED, and THERMINIC. PROFIT finished in March 2003. The project aimed at creating methods and tools to enable a sufficiently accurate measurement and prediction of temperature gradients in time and space required for a more accurate and timely assessment of cost, performance, safety, and reliability of electronic products in all stages of the product realization process. The PROFIT partners produced 55 deliverables and 83 conference and journal papers. The paper discusses some highlights of the project and indicates shortly their potential for small-scale applications.

Numerical predictive accuracy is assessed for component-printed circuit board (PCB) heat transfer in forced convection using a widely used computational fluid dynamics (CFD) software. In Part I of this paper, the benchmark test cases, experimental methods and numerical models were described. Component junction temperature prediction accuracy for the populated board case is typically within ±5°C or ±10%, which would not be sufficient for temperature predictions to be used as boundary conditions for subsequent reliability and electrical performance analyses. Neither the laminar or turbulent flow model resolve the complete flow field, suggesting the need for a turbulence model capable of modeling transition. The full complexity of component thermal interaction is shown not to be fully captured.

Thermo-mechanical reliability in advanced electronic packaging requires new materials testing approaches. The necessary understanding of the impact of very local material stressing on component reliability leads to the need of materials testing and characterization on microscopic scale. For example, defect initiation and propagation in multilayer structures as in WLP and flip chip technology, the influence of material migration to mechanical behavior or defect development in ultra-thin silicon dies often are not well understood. A key for micro materials testing and characterization is the measurement of strains and displacements inside microscopic regions. Correlation techniques (e.g., microDAC, nanoDAC) are one of the promising tools for that purpose. Their application potentials to micro testing for electronic packaging materials are demonstrated in the paper. More in detail, CTE measurement and crack testing are discussed. First attempts for testing under AFM conditions and their results are considered.

Reducing integrated circuit (IC) plastic packaging production costs by improving the transfer mold and leadframe designs is a costly and time-consuming process. Rather than building mold and leadframe prototypes to perform empirical studies, this research describes how C-MOLD, a microchip encapsulation simulation software application, was used to validate and optimize an innovative mold and leadframe design that has the potential to reduce raw material waste associated with packaging by more than 59 percent. Estimates indicate that the proposed design will cut annual production costs by more than $600,000.

Many systems composed of both hardware and software components are expected to be failure-free. This article discusses software reliability and presents the reader with an understanding of why it is meaningful to talk in terms of the reliability of software components. Software faults, unlike hardware faults, are not related to the physical properties of the components. They are the products of the design processes and software’s interfaces to other parts of the system. Just how well the software handles software and hardware faults to prevent errors from occurring determines how reliable the software and the system are deemed to be. [S1043-7398(00)00304-2]

This paper presents, discusses, and compares results from experimental and computational studies of the plastic encapsulation process for a 144-lead TQFP package. The experimental results were obtained using an instrumented molding press, while the computational predictions were obtained using a newly-developed software for modeling transfer molding processes. Validation of the software is emphasized, and this was done mainly by comparing the computational results with the corresponding experimental measurements for pressure, temperature, and flow front advancement in the cavities and runners. The experimental and computational results were found to be in good agreement, especially for the flow-front shapes and locations. [S1043-7398(00)00502-8]

The failure of electrical devices associated with solder joints has become one of the most critical reliability issues for surface-mounted devices. Solder joint reliability performance has been found to be highly dependent on the solder joint configuration, which, in turn, is governed by bond pad size, alloy material, and leadframe structure, as well as solder reflow characteristics. To investigate tombstone effects causing solder joint failure during leadless component reflow process, this work has focused on (1) developing a numerical model for the simulations of the solder joint formation during the reflow process, and (2) determining possibility that a tombstone effect for the leadless component may occur by analyzing the force and torque in the problem. Using this methodology, the tombstone effect associated with different pad geometry configurations and solder paste amount has been analyzed through the application of the public domain software tool Surface Evolver. Simulations show that the tombstoning is very sensitive to pad/component geometry design, solder surface tension, solder paste volume, wetting area, and wetting angle. This model simulation can be used to determine optimal solder paste volume, pad geometry configurations, and solder material for avoiding tombstone effects.

The relationships between the force measured during wetting balance tests and the observed changes of contact angle and meniscus shape are studied. Experiments using silicone oil at 25, 50, and 100°C on glass plates as well as Pb-Sn eutectic solder on Au-coated glass plates are reported. Discrepancies between the measured force and height and those expected for a static meniscus are detailed. Equilibrium meniscus shapes are computed for wide plates using the elastica solution and for narrow plates using the public-domain software package, “Surface Evolver.” For room temperature experiments with oil, the measured force discrepancy disappears when the meniscus rise is complete. Thus, the force discrepancy may be due to shear stress exerted on the sample by fluid rising up the sample. For static menisci with heated liquids, force and meniscus height discrepancies do not disappear when the meniscus rise is complete. These discrepancies can be explained by Marangoni flow due to temperature gradients in the fluid for the oil experiments but not for the solder experiments.

The ability of solder joint life-prediction algorithms to predict the failure of solder joints due to temperature-cycling induced creep-fatigue has been investigated using representative leadless chip carriers (LCCs) as the test vehicle. Four different algorithms are assessed: the classic Coffin-Manson algorithm, a modified Coffin-Manson algorithm with dependency on peak stress, and two strain-energy based algorithms. JPL’s special purpose nonlinear finite element computer program was used to dynamically simulate the solder joint response to the standard NASA temperature cycling environment, which ranges from −55°C to +100°C with a 4-hour period. The computed stress-strain history provided the inputs needed by each of the failure algorithms. To test the accuracy of the analytical predictions, three different sizes of LCCs (68 pins, 28 pins, and 20 pins) were subjected to an experimental test program using the same 4-hour temperature cycle as used in the analytical predictions. The three different sized ceramic packages, each with a 50-mil pitch, provided a range of cyclic strain ranges and solder fillet geometries so as to test the algorithms against realistic electronic packaging variables. The study highlights limitations in the historical Coffin-Manson relationship, and points up possible improvements associated with incorporating a stress modifier into the Coffin-Manson equation. This modification is also somewhat simpler and more accurate than the energy-density based algorithms, which also performed quite well.

Three-dimensional finite element analysis has been applied for determining time-dependent solder joint response of leaded surface mount components under thermal cycling. Two main challenges are the geometric complexity in mesh development and computationally intensive analysis because of the highly nonlinear material properties. Advanced techniques have been applied, including multi-point constraints for mesh transition, which reduces the number of degrees of freedom in the model, and substructuring, which effectively reduces computational time in the iterative analysis. The result is a generic approach for nonlinear creep analysis using commercial FEA software on a high performance workstation. Illustrations are provided for J and gullwing leaded packages.

A general design methodology for the optimal design of electronic packages is presented. The design problem is cast as a nonlinear programming (NLP) problem. Design for critical packaging issues such as thermal and mechanical performance, is automated by combining thermal and mechanical finite element analysis with an NLP optimizer. The major issues such as design problem formulation, model generation or preprocessing, nonlinear finite element analysis, design variable identification, design sensitivity analysis and software implementation are addressed. A case study involving the design of an RF packaging component in communication products illustrates the design methodology implemented in the Automated Design of Electronic Packaging (ADEP) software system.

Differential expansion induced creep-fatigue resulting from temperature cycling is an important cause of solder joint failure. The deterioration of solder joint integrity typically involves a sequential development of local stressing, microcracks, crack initiation and crack propagation, ultimately resulting in electrical open-circuiting by total joint separation from the PWB footprint. To better understand the failure process, a series of combined analytical and experimental investigations have been performed on flat-pack parts with gull-wing leads ranging in height from 9 to 56 mils. JPL’s special purpose nonlinear finite element computer program has been modified to dynamically simulate the crack propagation process. Solder creep properties, including the effect of grain growth, are also incorporated into the model. Depending upon the system geometry and materials properties, the combination of crack development and grain growth may have either a positive or negative effect on the rate of cracking of the solder elements. Consequently, the crack propagation process may accelerate or decelerate as cycles progress. Sensitivity studies are used to highlight the individual effects of crack propagation and grain growth and compare the failure prediction results with those obtained using conventional finite element techniques. The analytical results are corroborated using visual observations obtained using SEM photography of test samples exposed to the thermal-cycle environment used in the analysis.

An analytical model of solder joint formation during a surface mount reflow process is developed for two-dimensional fillets whose flow may be restricted due to “finite” metallizations on a leadless component and the printed circuit board. Although these height and length constraints on the fillet geometry may result in obtuse contact angles, the solution is obtained in the form of an explicit integral, similar to that previously derived by the authors for the case of acute contact angles. This solution may also be recast into the form of elliptic integrals of the first and second kinds, thereby permitting one to evaluate the fillet geometry using mathematical tables or special function software, if desired, rather than resorting to a computer-based numerical quadrature. In addition an approximate zero-gravity solution is given by means of simple closed-form expressions relating the height, length, contact angles, and cross-sectional area of the fillet. Numerical results generated by implementing the “exact” integral solution for the joint profile are given in the form of dimensionless plots, relating fillet geometry to the solder properties (surface tension and density), amount of solder, chip height, and pad length. Also presented in dimensionless form are the approximate results from the zero-gravity model, which are independent of solder properties, yet are of sufficient accuracy for “small” joints. Because of their dimensionless nature, the results of the present paper may be of maximum utility to process engineers aiming to achieve desired joint geometries (e.g., to maximize fatigue life or to eliminate bridging problems), or to board designers responsible for selecting efficient footprint patterns to maximize board density. Models of solder joint formation, such as the one presented here, may be of most value when used in conjunction with stress analysis packages (e.g., finite element programs) and appropriate fatigue models. In this way an integrated approach to the design of solder joints and circuit boards may be taken, resulting in improved product reliability and performance.

Parametric studies are performed on heat transfer in surface-mounted components of conduction cooled Standard Electronic Modules (SEMs). Thermal network models are developed for the various components that are used in the SEMs. The models are validated by comparing the results with available experimental results from various test modules. An interfacing software package for thermal analysis (IN-STAN) is used to generate the thermal network representations of the models and a thermal network analyzer is used to perform the analysis. Several studies are performed to analyze the effects of important thermal design parameters including: chip and carrier size, cavity floor thickness, air gap thickness, die and carrier materials, and solder material.

With flexible leaded parts, the solder-joint failure process involves a complex interplay of creep and fatigue mechanisms. To better understand the role of creep in typical multi-hour cyclic loading conditions, a specialized non-linear finite-element creep simulation computer program has been formulated. The numerical algorithm includes the complete part-lead-solder-PWB system, accounting for strain-rate dependence of creep on applied stress and temperature, and the role of the part-lead dimensions and flexibility that determine the total creep deflection (solder strain range) during stress relaxation. The computer program has been used to explore the effects of various solder creep-fatigue parameters such as lead height and stiffness, thermal-cycle test profile, and part/board differential thermal expansion properties. One of the most interesting findings is the strong presence of unidirectional creep-ratcheting that occurs during thermal cycling due to temperature dominated strain-rate effects. To corroborate the solder fatigue model predictions, a number of carefully controlled thermal-cycle tests have been conducted using special bimetallic test boards.

The spacecraft electronic assemblies are subjected to severe environmental conditions during testing, launching and during orbit mission. The success of the mission depends upon the proper functioning of these critical electronic modules. The structural analyses using Finite Element Methods (FEM) assure the integrity of these components. A typical box, Array Drive Electronics (ADE), for TIROS satellites [1] is discussed in this article. The NASTRAN software was used to perform the stress and modal analyses of the box assembly with five circuit boards, covers and mounting feet. The stress analysis was performed for a static solution. As a conservative loading, 3 sigma load factor was used in the calculation of the acceleration values from the random vibration test conditions. Margins of safety were calculated. Design and material changes were recommended. The mode shapes fall in to three groups as explained in the text.