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Keywords: Chip stacking
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Journal Articles
Article Type: Review Articles
J. Electron. Packag. June 2022, 144(2): 020801.
Paper No: EP-21-1008
Published Online: September 24, 2021
... a business platform to propel continuous innovation and performance improvement extending to surveillance, medical, and automotive industries. This overview briefs the general camera module and the crucial technology elements of chip stacking architectures and advanced interconnect technologies. This study...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. December 2018, 140(4): 041002.
Paper No: EP-18-1007
Published Online: August 3, 2018
... is scalable and has the same guiding value for multichip stacks with different functions and constraints. A setup of four-chip stack is used to demonstrate the feasibility of this optimization and a large TSV area saving is achieved by this method. References [1] Shen , W. , Lin , Y. , Chen...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. March 2018, 140(1): 010905.
Paper No: EP-17-1099
Published Online: March 2, 2018
... . Manuscript received September 27, 2017; final manuscript received December 28, 2017; published online March 2, 2018. Assoc. Editor: Sreekant Narumanchi. 27 09 2017 28 12 2017 3D packaging Chip stacking Harsh environment Thermal analysis The adequate selection...
Journal Articles
Article Type: Review Articles
J. Electron. Packag. March 2018, 140(1): 010801.
Paper No: EP-17-1076
Published Online: March 2, 2018
... Bumping Chip stacking The concealed force behind the successful journey from information technology toward internet of things is the rapid progress in accommodating more functionality with a single silicon chip. This improvement in integrated circuit (IC) performance was primarily achieved...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. December 2017, 139(4): 041004.
Paper No: EP-17-1044
Published Online: September 5, 2017
... and Photonic Packaging Division of ASME for publication in the J OURNAL OF E LECTRONIC P ACKAGING . Manuscript received April 25, 2017; final manuscript received July 26, 2017; published online September 5, 2017. Assoc. Editor: Yi-Shao Lai. 25 04 2017 26 07 2017 Chip stacking Flip chip...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. September 2017, 139(3): 031004.
Paper No: EP-16-1110
Published Online: June 14, 2017
... Conference on High Density Microsystem Design and Packaging and Component Failure Analysis ( HDP ), Shanghai, China, June 27–30, pp. 242 – 246 . 10.1109/HDP.2006.1707600 3D packaging Area array Chip stacking Failure analysis High density interconnects Microsystems In two-dimensional...
Journal Articles
Article Type: Guest Editorial
J. Electron. Packag. June 2017, 139(2): 020301.
Paper No: EP-17-1032
Published Online: June 12, 2017
...Justin A. Weibel; S. Ravi Annapragada 22 03 2017 31 03 2017 3D packaging Backplanes Chip stacking Failure analysis Flexible circuits Nanotechnolgy Reliability Solder Thermal analysis Underfill Wafer level packaging ASME's International Mechanical Engineering...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. June 2017, 139(2): 020908.
Paper No: EP-16-1140
Published Online: June 12, 2017
... Division of ASME for publication in the J OURNAL OF E LECTRONIC P ACKAGING . Manuscript received December 16, 2016; final manuscript received March 27, 2017; published online June 12, 2017. Assoc. Editor: Justin A. Weibel. 16 12 2016 27 03 2017 3D packaging Chip stacking Thermal...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. March 2017, 139(1): 011008.
Paper No: EP-16-1096
Published Online: January 10, 2017
... thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance. 1 Corresponding author. Contributed by the Electronic and Photonic Packaging Division of ASME...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. March 2017, 139(1): 011001.
Paper No: EP-16-1073
Published Online: November 10, 2016
... . Manuscript received June 14, 2016; final manuscript received October 25, 2016; published online November 10, 2016. Assoc. Editor: Mehdi Asheghi. 14 06 2016 25 10 2016 Chip stacking Failure analysis Harsh environment Micro vias SOC Thermal analysis Gallium nitride (GaN) based...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. December 2016, 138(4): 041009.
Paper No: EP-16-1090
Published Online: October 21, 2016
...Thomas Brunschwiler; Jonas Zürcher; Luca Del Carro; Gerd Schlottig; Brian Burg; Severin Zimmermann; Uwe Zschenderlein; Bernhard Wunderle; Florian Schindler-Saefkow; Rahel Stässle Heat dissipation from three-dimensional (3D) chip stacks can cause large thermal gradients due to the accumulation...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. September 2016, 138(3): 031006.
Paper No: EP-15-1054
Published Online: June 28, 2016
... . Manuscript received May 26, 2015; final manuscript received June 13, 2016; published online June 28, 2016. Assoc. Editor: Shi-Wei Ricky Lee. 26 05 2015 13 06 2016 3D packaging Chip stacking Failure analysis The three-dimensional integrated circuit (3D IC) is an emerging...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. March 2016, 138(1): 010909.
Paper No: EP-15-1097
Published Online: March 11, 2016
...Michael Fish; Patrick McCluskey; Avram Bar-Cohen As thermal management techniques for three-dimensional (3D) chip stacks and other high-power density electronic packages continue to evolve, interest in the thermal pathways across substrates containing a multitude of conductive vias has increased...
Journal Articles
Article Type: Technical Briefs
J. Electron. Packag. December 2015, 137(4): 044501.
Paper No: EP-15-1062
Published Online: October 20, 2015
... , “ Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack ,” ASME J. Electron. Packag. , 137 ( 2 ), p. 021011 . 10.1115/1.4029345 [5] Sun , Y. , Thompson , S. E. , and Nishida , T. , 2007 , “ Physics of Strain Effects...
Journal Articles
Article Type: Review Articles
J. Electron. Packag. December 2015, 137(4): 040802.
Paper No: EP-15-1068
Published Online: September 25, 2015
.... Editor: Mehdi Asheghi. 22 07 2015 30 08 2015 3D packaging Chip stacking Failure analysis Physics of failure Thermal analysis Three-dimensional interconnect technology promises significant performance advantages for the next generation of computing and communications...
Journal Articles
Article Type: Research-Article
J. Electron. Packag. September 2015, 137(3): 031007.
Paper No: EP-14-1083
Published Online: September 1, 2015
... of thermal expansion (CTE) were assessed for a chip stacking architecture. The microbumps for integrating four chips on a Si interposer were with a pitch size of 20  μ m and composed of 5  μ m Cu/3  μ m Ni/5  μ m Sn2.5Ag solder cap. A thermocompressive bonder was used to interconnect the microbumps at 280 °C...
Journal Articles
Article Type: Research Papers
J. Electron. Packag. December 2009, 131(4): 041007.
Published Online: October 29, 2009
... moduli finite element analysis gold integrated circuit bonding integrated circuit interconnections stress effects ultrasonic bonding flip chip bumping chip stacking chip on board manufacturing technology finite elements stress analysis micromechanics Research interest...